Toshiba is sampling 64-layer 3-bit-per cell 512Gbit 3D NAND. Mass production is scheduled for H2. In April Toshiba plans to sample a 1Tbyte product which stacks 16 512Gbit die in a package. For the 512Gbit device, Toshiba deployed a 64-layer stacking process to realize a 65% larger capacity per unit chip size than the 48-layer 256Gbit ...
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